library verilog;
use verilog.vl_types.all;
entity DES_top is
    port(
        Text_Input      : in     vl_logic_vector(64 downto 1);
        Key_Input       : in     vl_logic_vector(64 downto 1);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        Final_Result    : out    vl_logic_vector(64 downto 1);
        State_For_Tb    : out    vl_logic_vector(4 downto 1);
        Round_for_Tb    : out    vl_logic_vector(4 downto 1);
        Initial_Permutation_Output: out    vl_logic_vector(64 downto 1);
        PC1_Left        : out    vl_logic_vector(28 downto 1);
        PC1_Right       : out    vl_logic_vector(28 downto 1);
        Key_Left        : out    vl_logic_vector(28 downto 1);
        Key_Right       : out    vl_logic_vector(28 downto 1);
        Left_Shift1_Left_Output: out    vl_logic_vector(28 downto 1);
        Left_Shift1_Right_Output: out    vl_logic_vector(28 downto 1);
        Left_Shift2_Left_Output: out    vl_logic_vector(28 downto 1);
        Left_Shift2_Right_Output: out    vl_logic_vector(28 downto 1);
        Permuted_Choice_2_Output: out    vl_logic_vector(48 downto 1);
        Expansion_Function_Output: out    vl_logic_vector(48 downto 1);
        Left_Right_Swap_Input_Left: out    vl_logic_vector(32 downto 1);
        Left_Right_Swap_Input_Right: out    vl_logic_vector(32 downto 1);
        XOR32_Output    : out    vl_logic_vector(32 downto 1);
        Permutation_Output: out    vl_logic_vector(32 downto 1);
        Final_Permutation_Output: out    vl_logic_vector(64 downto 1)
    );
end DES_top;
